An SRAM is typically designed to store many thousands of bits of information. These bits are stored in individual memory cells that are organized into rows and columns to make efficient use of space on a semiconductor substrate in an integrated circuit. A basic storage element is the six transistor SRAM cell, which may be written into and read from under SRAM control. In SRAM arrays having interleaved words in a same row, some of the six transistor storage cells are subject to being upset when reading from fully-addressed cells. An asymmetric SRAM cell may be employed where the cell is constructed to be more stable during a read operation. However, making the cell more stable during the read operation makes it more difficult to perform a write operation into the cell. Improvements in this area would prove beneficial in the art.